The output stages of power amplifiers are normally designed for maximizing the dynamic excursion of the output voltage (output voltage swing), by reducing as much as possible voltage drops due to the series resistance of the active components (transistors) that form the output stage. There is an ample specific bibliography out of which the volume "Power Integrated Circuit", published by Mc.Graw Hill, in 1986, pages 9.28-9.35 may be cited.
A widely used technique in power output stages is that of realizing a "bootstrap" line, using for this purpose a relatively large capacitance, that may be externally connected to the IC pins, in order to obtain the maximum peak-to-peak variation of the output voltage. Unfortunately, this technique conflicts with a general IC design trend of eliminating or reducing the need of passive external components to a minimum.
The known configurations of a power output stage are amply reported in literature and substantially are those employing a pair of transistors operating in phase opposition, namely an NPN/NPN, PNP/NPN, pMOS/nMOS and nMOS/nMOS pair. Of course, the selection of one of the above configurations depends on the fabrication technology that is employed, which determines also the maximum reverse voltage that can be withstood by the devices (for example the maximum VCE of bipolar junction transistors or the maximum VDS of MOS transistors).
Bipolar NPN transistors notably suffer from the problem connected to the so-called "secondary breakdown" phenomenon. Also bipolar PNP transistors are affected by this phenomenon but in a lesser measure than NPN transistors.
On the contrary, DMOS transistors are notably exempt from this problem.
In a mixed technology fabrication process (BJT, CMOS and DMOS) or BCD process, the power MOS transistors that can be realized in a compatible manner with the other type of integrated structures, have internal resistance characteristics that typically show the following values:
(n-channel) DMOS: Ron=0.5 .OMEGA..times.mm.sup.2 PA1 (p-channel) DMOS: Ron=2.2 .OMEGA..times.mm.sup.2
In particular, the solution of using a complementary pair of DMOS output transistors would appear an ideal choice, by considering also the advantage represented by the fact that the two output transistors would not need a driving current, being intrinsically voltage-controlled devices. However, a p-channel DMOS transistor requires an integration area that may be four times the integration area of an n-channel, complementary DMOS transistor, for the same Ron. Therefore the solution that employs a complementary pair of DMOS transistors is adopted only in a limited number of applications, where the relatively large silicon area requirement is not a problem.
On the other hand, the use of a (more compact) pair of transistors of the same polarity (that is noncomplementary), for example a pair of n-channel DMOS transistors, besides losing a portion equivalent to a VGS voltage of the maximum voltage swing of the output signal or otherwise requiring a bootstrap line, requires also a somewhat more complex driving circuit than the circuit that would be necessary for driving, in phase opposition, a complementary pair of output transistors.
There is a long felt need or utility of a complementary output stage with good breakdown characteristics that would not need externally connected bootstrap components and require a relatively large area of integration.